A Dynamically Reconfigurable Highly Scalable Multiplier with Reusable, Locally Optimized Structures


A large bit width multiplier with multiple copies of a core small bit width multiplier and ROM cells. The present invention provides a power system that trades off processing speed against power dissipation. The present invention reduces power dissipation to about half of the best industry implementation at about half the speed. Its power dissipation is 10% of another industry standard implementation at 1.5 times the speed. The present invention has a gate count that is about twice the gate count for these implementations.

Patent Information:
Computer Science
For Information, Contact:
Dana Vouglitois
Florida Atlantic University
Ravi Shankar
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